Confirmed Talks

Programme

Event Recording

Programme Overview

• 14:40-15:20 : Prof. Wayne Luk, Imperial College London

  Title:

  Recent Advances in Reconfigurable Machine Learning Acceleration

  Abstract:

  Rapid progress has been made in the development of reconfigurable architectures for accelerating a wide variety of machine learning techniques. This talk describes recent advances in developing such architectures, focusing on those that target field programmable technology. The talk covers optimisations for enhancing performance of recurrent neural networks and Bayesian neural networks, as well as methods for co-optimising a neural network and its hardware implementation. There will be an illustration of future development tools for machine learning architectures, supporting not just top-down synthesis but also bottom-up diagnosis.

  Bio:

  Wayne Luk is Professor of Computer Engineering at Imperial College London, and was Visiting Professor at Stanford University. His research interests include custom computing, machine learning technology, and reconfigurable systems. Many of his papers received awards from the ASAP, FCCM, FPL and FPT conferences, and he also won a Research Excellence Award from Imperial College London. He is a Fellow of the IEEE, the BCS, and the Royal Academy of Engineering.



• 15:20-16:00 : Prof. Deming Chen, Univ of Illinois, Urbana-Champaign

  Title:

  Design of Reconfigurable Computing Systems for Smart IoT Applications

  Abstract:

  Many new IoT (Internet of Things) applications are driven by the fast creation, adaptation, and enhancement of various types of Deep Neural Networks (DNNs). DNNs are computation intensive. Without efficient hardware implementations of DNNs, these promising IoT applications will not be practically realizable. In this talk, we will analyze several challenges facing the AI and IoT community for mapping DNNs to hardware accelerators. Especially, we will evaluate FPGA's role for accelerating DNNs targeting both cloud and edge computing. We will present a series of effective design techniques for implementing DNNs on FPGAs with high performance, energy efficiency and adaptability. These include automated DNN/FPGA co-design, smart reuse of configurable DNN IPs, smart pipeline scheduling, Winograd techniques, and DNN quantization. The design flows developed based on the proposed techniques, such as DNNBuilder, have been adopted by the industry (e.g., IBM and Xilinx). The new DNN models produced, such as SkyNet, have won championships in the competitive DAC System Design Contest for low-power object detection.

  Bio:

  Dr. Deming Chen obtained his BS in computer science from University of Pittsburgh, Pennsylvania in 1995, and his MS and PhD in computer science from University of California at Los Angeles in 2001 and 2005 respectively. He joined the ECE department of University of Illinois at Urbana-Champaign in 2005. His current research interests include reconfigurable computing, machine learning and cognitive computing, hybrid cloud, system-level and high-level synthesis, and hardware security. He has given more than 120 invited talks sharing these research results worldwide. He has received 9 Best Paper Awards, a few Best Poster Awards, and numerous other research and service related awards. He is the Donald Willett Faculty Scholar and the Abel Bliss Professor of the Grainger College of Engineering, an IEEE Fellow, an ACM Distinguished Speaker, and the Editor-in-Chief of ACM Transactions on Reconfigurable Technology and Systems (TRETS).



• 16:10:16:50 : Prof. Vanderlei Bonato, The University of Sao Paulo

  Title:

  Class-specific Early Exit Design Methodology for Convolutional Neural Networks

  Abstract:

  In this talk, we present a method for designing early-exit networks from a given baseline model aiming to improve the average latency for a targeted subset class constrained by the original accuracy for all classes. Results are demonstrated for dataset CIFAR10 and CIFAR100 using the baseline models ResNet-21, ResNet-110, Inceptionv3-159, and DenseNet-121. Initial results of mapping early-exit networks to the kernel-orientated platform Xilinx DNNDK 3.1 are also demonstrated.

  Bio:

  Vanderlei Bonato is an associate professor of the Institute of Mathematics and Computer Sciences at The University of Sao Paulo (ICMC-USP), Brazil. His interest areas are hardware architecture design, modeling and synthesis tools for FPGAs. Vanderlei Bonato has served the committee of several events, including ARC, HiPEAC-WRC, WSCAD, ERAD-SP, SBESC, FEEC, and etc. He has also served as ad-hoc reviewer of the journals IEEE TCSVT, IEEE TVLSI, IEEE TIP, MICPRO, JSA, and etc. He is an Associate Editor of the Int. J. of Embedded Systems (IJES).



• 16:50-17:30 : Prof. Viktor Prasanna, University of Southern California

  Title:

  ​​Accelerating Graph Neural Networks using FPGAs

  Abstract:

  Recently, Graph Neural Networks (GNNs) have been used in many applications leading to improved accuracy and fast approximate solutions. Training as well as Inference in these networks is computationally demanding. Challenges include access to irregular data, sparse as well as dense matrix computations, limited data reuse and heterogeneity in the various stages of the computation. With recent dramatic advances in Field Programmable Gate Arrays (FPGAs), these devices are being used along with multi-core and novel memory technologies to realize advanced platforms to accelerate complex applications. This talk will review our recent work in the Data Science Lab at USC (dslab.usc.edu) and advances in reconfigurable computing (fpga.usc.edu) leading up to current trends in accelerators for data science. For graph embedding, we develop GraphSAINT, a novel computationally efficient technique using graph sampling and demonstrate scalable performance. We develop graph processing over partitions (GPOP) methodology to handle large scale graphs on parallel platforms. On a current FPGA device, we demonstrate up to 100X and 30X speed up for full graph GNN computational steps compared with state of the art implementations on CPU and GPU respectively. We also demonstrate specific accelerators for two widely used GNN models: GraphSAGE and GraphSAINT. We conclude by identifying opportunities and challenges in exploiting emerging heterogeneous architectures composed of multi-core processors, FPGAs, GPUs and coherent memory.

  Bio:

  Viktor K. Prasanna (ceng.usc.edu/~prasanna) is Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical and Computer Engineering and Professor of Computer Science at the University of Southern California. He is the director of the Center for Energy Informatics at USC and leads the FPGA (fpga.usc.edu) and Data Science Labs (dslab.usc.edu). His research interests include parallel and distributed computing, accelerator design, reconfigurable architectures and algorithms and high performance computing. He served as the Editor-in-Chief of the IEEE Transactions on Computers during 2003-06 and is currently the Editor-in-Chief of the Journal of Parallel and Distributed Computing. Prasanna was the founding Chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is the Steering Chair of the IEEE International Parallel and Distributed Processing Symposium and the Steering Chair of the IEEE International Conference on High Performance Computing. His work has received best paper awards at leading forums in parallel computing, HPC and FPGAs, including ACM/IEEE Computing Frontiers, International Parallel and Distributed Processing Symposium, ACM International Symposium on FPGAs, among others. He is a Fellow of the IEEE, the ACM and the American Association for Advancement of Science (AAAS). He is a recipient of 2009 Outstanding Engineering Alumnus Award from the Pennsylvania State University and a 2019 Distinguished Alumnus Award from the Indian Institute of Science. He received the 2015 W. Wallace McDowell award from the IEEE Computer Society for his contributions to reconfigurable computing.



• 17:30-18:10 : Prof. Stjepan Picek, TU Delft

  Title:

  Machine Learning and Side-channel Analysis

  Abstract:

  In side-channel analysis (SCA), the attacker exploits weaknesses in the physical implementations of cryptographic algorithms. This talk investigates how machine learning in profiling side-channel analysis can break various implementations even protected with countermeasures. After discussing several success stories, we concentrate on critical open questions and research directions that still need to be explored. Finally, we briefly connect the machine learning progress in SCA with developments in other security domains.

  Bio:

  Stjepan Picek is an assistant professor in the Cybersecurity group at TU Delft, The Netherlands. His research interests are security/cryptography, machine learning, and evolutionary computation. Before the assistant professor position, Stjepan was a postdoctoral researcher at MIT, USA, and at KU Leuven, Belgium. Stjepan finished his PhD in 2015 with a topic on cryptology and evolutionary computation. Stjepan is a member of the International Summer School in Cryptography organization committee and a general co-chair for Eurocrypt 2021.

• Closing Remarks